Narrow trenches are commonly desired during fabrication of a wide array of semiconductor devices. Hence, although a specific example concerning the utility of narrow trenches is discussed below in connection with trench MOSFET devices, it is noted that narrow trenches have utility throughout the semiconductor field.
A trench MOSFET (metal-oxide-semiconductor field-effect transistor) is a transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin insulator layer such as an oxide layer and filled with a conductor such as polysilicon (i.e., polycrystalline silicon), allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench MOSFET transistors are disclosed, for example, in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931, the disclosures of which are hereby incorporated by reference.
As a specific example, FIG. 1 illustrates half of a hexagonally shaped trench MOSFET structure 21 disclosed in U.S. Pat. No. 5,072,266. The structure includes an n+ substrate 23, upon which is grown a lightly doped n epitaxial layer 25 of a predetermined depth depi. Within the epitaxial layer 25, p body region 27 (p, p+) is provided. In the design shown, the p body region 27 is substantially planar (except in a central region) and typically lays a distance dmin below the top surface of the epitaxial layer. Another layer 28 (n+) overlying most of the p body region 27 serves as source for the device. A series of hexagonally shaped trenches 29 are provided in the epitaxial layer, opening toward the top and having a predetermined depth dtr. The trenches 29 are typically lined with oxide and filled with conductive polysilicon, forming the gate for the MOSFET device. The trenches 29 define cell regions 31 that are also hexagonally shaped in horizontal cross-section. Within the cell region 31, the p body region 27 rises to the top surface of the epitaxial layer and forms an exposed pattern 33 in a horizontal cross section at the top surface of the cell region 31. In the specific design illustrated, the p+ central portion of the p body region 27 extends to a depth dmax below the surface of the epitaxial layer that is greater than the trench depth dtr for the transistor cell so that breakdown voltage is away from the trench surface and into the bulk of the semiconductor material.
A typical MOSFET device includes numerous individual MOSFET cells that are fabricated in parallel within a single chip (i.e., a section of a semiconductor wafer). Hence, the chip shown in FIG. 1 contains numerous hexagonal-shaped cells 31 (portions of five of these cells are illustrated). Cell configurations other than hexagonal configurations are commonly used, including square-shaped configurations. In a design like that shown in FIG. 1, the substrate region 23 acts as a common drain contact for all of the individual MOSFET cells 31. Although not illustrated, all the sources for the MOSFET cells 31 are typically shorted together via a metal source contact that is disposed on top of the n+ source regions 28. An insulating region, such as borophosphosilicate glass (not shown) is typically placed between the polysilicon in the trenches 29 and the metal source contact to prevent the gate regions from being shorted with the source regions. Consequently, to make gate contact, the polysilicon within the trenches 29 is typically extended into a termination region beyond the MOSFET cells 31, where a metal gate contact is provided on the polysilicon. Since the polysilicon gate regions are interconnected with one another via the trenches, this arrangement provides a single gate contact for all the gate regions of the device. As a result of this scheme, even though the chip contains a matrix of individual transistor cells 31, these cells 31 behave as a single large transistor.
Demand persists for trench MOSFET devices having ever-lower on-resistance. One way to reduce on-resistance is to increase cell density. Unfortunately, the gate charges associated with trench MOSFET devices also increase when cell density is increased. As a result, steps need to be taken to reduce such gate charges. As noted in JP05335582, the oxide film at the trench sidewall of a trench MOSFET device forms the channel within the P-body region. The oxide film at the bottom of the trench, on the other hand, does not contribute significantly to channel formation, but nonetheless contributes to gate charges. The inventors in JP05335582 propose thickening the oxide film at the bottom of the trench substantially relative to the oxide film at the sidewall to reduce gate charges.
A related way to reduce the gate charge contribution of the trench bottoms is to provide narrower trenches, as is known in the art. The present invention provides a novel process for the formation of narrow trenches within a semiconductor substrate.